Chips Are Approaching the Size of Atoms — Japan's Invisible Moat in the AI Supply Chain

This is Part 3 of the NVIDIA Series. Part 1 is here, Part 2 is here.

The Shotgun Formation Has a Physics Problem

Part 1 introduced the GPU as a shotgun formation — a hundred receivers running routes simultaneously instead of one player going it alone.

That analogy raises an obvious question: where do you put all those receivers?

A modern GPU contains tens of billions of transistors — the microscopic switches that perform each individual calculation. More parallel processing means more transistors. More transistors means fitting more of them into the same physical space. And the only way to do that is to make each transistor smaller.

NVIDIA's H100 GPU, the current workhorse of enterprise AI, is manufactured on TSMC's 4-nanometer process. The next generation moves to 3 nanometers.

One nanometer is one-billionth of a meter. A human hair is approximately 80,000 nanometers wide. A 4-nanometer transistor is roughly 1/20,000th the width of a human hair. A silicon atom is about 0.2 nanometers — meaning today's transistors are only about twenty atoms across.

This is not a figure of speech. Semiconductor manufacturing has reached the practical limits of atomic-scale engineering.

Why Miniaturization Cannot Stop

AI model complexity is growing faster than computing efficiency.

GPT-3 (2020): 175 billion parameters. GPT-4: estimated 1 trillion parameters. Future models will be larger still. Running these models at commercially viable costs requires squeezing more computation per square millimeter of silicon every generation.

The alternative — making chips physically larger — doesn't work. A larger chip means signals must travel farther, increasing latency and heat. It's like expanding a football stadium to add seating but forgetting that the players still have to cover the whole field. The game slows down.

The semiconductor industry has no choice but to keep scaling down. And as dimensions shrink toward atomic scale, the precision required in every step of manufacturing becomes almost incomprehensibly demanding.

Building at Atomic Scale: What It Actually Takes

Fabricating a 3-nanometer chip requires:

A cleanroom 1,000 times cleaner than a hospital operating room. A single particle of dust landing on a wafer during production can destroy dozens of chips. Cleanrooms measure contamination in particles per cubic meter — and advanced fabs run at levels approaching zero. Workers wear full-body suits. Air is recycled and filtered continuously. Static electricity is actively suppressed.

Silicon of extraordinary purity. The silicon wafer that serves as the chip's substrate must be 99.999999999% pure — eleven nines. At 3 nanometers, even a single misplaced atom in the wrong location can cause a transistor to fail.

Photolithography at wavelengths shorter than visible light. Chip circuits are "drawn" on silicon using light. But 3-nanometer features are smaller than the wavelength of visible light — so manufacturers use extreme ultraviolet (EUV) light, which requires machines that cost $200 million each and can only be built by ASML in the Netherlands.

Chemical precision at molecular scale. Every material deposited, every etch, every exposure step must be precisely controlled to tolerances that didn't exist as engineering concepts thirty years ago.

Where Japan's Moat Is Hidden

This extreme manufacturing environment is where Japanese companies have built an almost invisible but extremely durable competitive position.

Silicon Wafers — Shin-Etsu Chemical (4063) and SUMCO (3436)

The raw silicon wafer is the foundation of every chip on earth. Shin-Etsu and SUMCO together supply approximately 60% of global wafer demand. Both companies have invested decades in the process chemistry required to achieve eleven-nine purity at commercial scale. New entrants face not just capital requirements but decades of accumulated process know-how that cannot be purchased or replicated quickly.

Photoresist — Shin-Etsu, JSR (4185), Tokyo Ohka Kogyo (4186)

Photoresist is the light-sensitive material applied to wafers before circuit patterns are exposed. At 3-nanometer scale, the chemistry must be uniform at the molecular level. Japanese companies control the majority of global supply for advanced photoresists. This is a market where customer switching costs are extremely high — any new material must be validated against the fab's entire process flow before adoption.

Manufacturing Equipment — Tokyo Electron (8035)

While ASML dominates EUV exposure equipment, the remainder of the fabrication process — deposition, etching, cleaning, inspection — involves dozens of distinct equipment categories. Tokyo Electron is among the top three suppliers globally across several of these categories. When TSMC announces a capacity expansion in response to AI demand, Tokyo Electron's order backlog lengthens in near-direct proportion.

Test Equipment — Advantest (6857)

Every chip must be tested before shipment. AI chips, with their billions of transistors operating under demanding conditions, require testing systems capable of detecting failures at extreme precision. Advantest holds roughly 50% global market share in semiconductor test equipment. As chip complexity grows — driven directly by AI requirements — the value of each test system sold increases.

The Structural Picture

Two observations worth holding:

First, these companies benefit from AI demand regardless of which AI model wins. OpenAI, Google, Meta, Chinese players — all of them require the same wafers, the same equipment, the same test systems. This is a toll-road business, not a winner-take-all bet.

Second, the barriers to competition are physical and cumulative. You cannot replicate eleven-nine silicon purity by hiring engineers away from Shin-Etsu. You cannot replicate Tokyo Electron's process knowledge by copying their equipment blueprints. These advantages compound over decades, not quarters.

Why This Is Distinct from a Simple AI Trade

Much of the AI-themed investing conversation focuses on software companies — the model developers, the application builders, the cloud platforms. These are businesses where competitive positions can shift quickly as technology evolves.

The Japanese supply chain sits in a different category. Whoever builds the next generation of AI infrastructure will need to manufacture it. That manufacturing requires precision materials and precision equipment. The companies capable of supplying both, at scale, at the required specifications, are few. And they are largely in Japan.

NVIDIA has a software moat in CUDA. Japan's materials and equipment companies have a physical moat in the accumulated engineering required to build at atomic scale. Both are difficult to breach. Both compound over time.

Part 4 — "Google's TPU: Counter-Attack or Sideshow?" — coming soon.

Source: Company IR materials and public filings | 日本語版

Disclaimer | This article is for informational purposes only and does not constitute investment advice. URL: analysis/2026/03/nvidia-ai-series-03/Save_As: analysis/2026/03/nvidia-ai-series-03/index.html